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Serial Quad I/O (SQI) Flash Memory
A Microchip Technology Company
SST26VF016 / SST26VF032
Data Sheet
Quad J-ID Read (SQI Protocol)
The Quad J-ID Read instruction identifies the devices as SST26VF016/032 and manufacturer as SST.
To execute a Quad J-ID operation the host drives CE# low and then sends the Quad J-ID command
cycle (AFH). Each cycle is two nibbles (clocks) long, most significant nibble first.
Immediately following the command cycle the device outputs data on the falling edge of the SCK sig-
nal. The data output stream is continuous until terminated by a low-to-high transition of CE#. The
device outputs three bytes of data: manufacturer, device type, and device ID, see Table 6. See Figure
14 for instruction sequence.
CE#
MODE 3
0
2
4
6
8
10
12
N
SCK
MODE 0
SIO(3:0)
C1 C0 H0 L0 H1 L1 H2 L2 H0 L0 H1 L4 H2 L2
MSN LSN
HN LN
BFH
26H
Device ID
BFH
26H
Device ID
N
1359 F39.0
Note: MSN = Most significant Nibble; LSN= Least Significant Nibble
C[1:0]=AFH
Figure 14: Quad J-ID Read Sequence
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 KByte sector to ‘1,’ but it does not change
a protected memory area. Prior to any write operation, the Write-Enable (WREN) instruction must be
executed.
To execute a Sector-Erase operation, the host drives CE# low, then sends the Sector Erase command
cycle (20H) and three address cycles, and then drives CE# high. Each cycle is two nibbles, or clocks,
long, most significant nibble first. Address bits [A MS :A 12 ] (A MS = Most Significant Address) determine
the sector address (SA X ); the remaining address bits can be V IL or V IH . Poll the BUSY bit in the Status
register or wait T SE for the completion of the internal, self-timed, Sector-Erase operat i on. See Figure
15 for the Sector-Erase sequence.
CE#
MODE 3
0
1
2
4
6
SCK
SIO(3:0)
MODE 0
C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
1359 F07.0
Note: MSN = Most Significant
Nibble, LSN = Least Signifi-
cant Nibble
Figure 15: 4 KByte Sector-Erase Sequence
?2011 Silicon Storage Technology, Inc.
19
DS-25017A
04/11
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